1. Field of the Invention
The present invention relates to integrated circuits; in particular, the present invention relates to “scale and bias” layout migration methods used to adapt a layout of an existing integrated circuit that is designed for fabrication by one manufacturing process to another, typically more advanced, manufacturing process.
2. Discussion of the Related Art
In the integrated circuit (IC) industry, a circuit design and its corresponding “layout” (i.e., the physical implementation1) are often migrated from one fabrication process to a different, often more advanced, fabrication process. When a layout is migrated to a newer fabrication process, the physical dimensions in the layout are scaled down to achieve a smaller “chip size” or footprint and better performance. The well-known Moore's law predicts a doubling of IC performance every 18 months. At the same time, the size of an IC chip for a given complexity would also decrease, as a result of advance in process technology. As more advanced processes use smaller feature sizes, a layout targeted for fabrication in one process may be re-targeted for fabrication in a newer or different process. The designer typically prefers to reuse an existing layout as much as possible, rather than having to redesign the layout from “scratch,” for time-to-market considerations, as the integrated circuit industry is under intense competition. 1A layout database that represents a layout is typically organized by layers, with each layer representing the image of a photo-lithographical mask. The image of each layer consists of a number of polygons that define areas through which light is allowed to pass or is occluded. The term “geometries” are also colloquially used for the polygons. In this description, the term “polygon” is used throughout interchangeably with the term “geometry.”
In digital circuits, advanced development in computer-aided-design (CAD) tools and the cell-based design methodology made possible extensive reuse of cell-based digital designs. In contrast, for custom circuit designs (i.e., designs that do not follow a cell-based design methodology), CAD tools still require significant amount of manual intervention. Often, custom circuit designers have to rely on their past experience and expertise to achieve a desired performance. Migrating a custom design to a new fabrication process, or to a new design specification, often involves manual redrawing of many parts—if not all—of the layouts. Naturally, such a process is both time consuming and tedious. Therefore, a methodology for automatically migrating a layout to a new fabrication process or a new design specification is important, especially in light of design and turn-around times reduction considerations.
In migrating a layout between fabrication processes, “scale and bias” is a technique that is often used. The technique is used, for example, in the lambda design rule system, which is part of the original VLSI design flow proposed by Mead and Conway more than 30 years ago. In the lambda design rule system, any feature in the layout can naturally be scaled and biased from one fabrication process to another sufficiently similar fabrication process. The technique relies on the assumption that all geometry in the layout scale proportionally. However, this assumption is valid only when the two fabrication processes are sufficiently similar, and when the design rules are conservative and not optimized. The resulting scaled layout typically requires a larger silicon area than is desirable, as some techniques used in the original process may not be able to take advantage of minimum size or spacing for some features or elements in the target process. Over time, the lambda design rule system is replaced by a more complicated “micron design rule system” which uses in the layout database the actual dimensions in the design rules for the target fabrication process.
Historically, influenced by Moore's law, successively generations of fabrication processes typically reduce area requirements by one-half. This reduction means that the X and Y dimensions are each reduced by around 30% or, essentially, a scaling factor of about 0.7. Often, a fabrication process of intermediate dimensions may also be provided. In that case, the generational process would be known as a “full node” process, while the intermediate dimension fabrication process is known as a “half node” process. Other than the difference in feature dimensions, the half node process is often a minor variation of the full node process. Under the scale and bias technique, a layout may be scaled from a “full node process” to a “half node” process through a proportional reduction that can be performed substantially automatically by computer during preparation of the photo-lithographical masks. For example, the 45 nm process is a full node process and 40 nm process is a half node process. The layout can be migrated from 45 nm to 40 nm through a “90% shrink.” The same reduction procedure can be performed for migrations from a 32 nm process to a 28 nm process and from a 22 nm process to a 20 nm process.
To illustrate a layout migration process, for a database resolution of 1 nm and a design grid unit of 1 nm, an edge in a polygon that is 23 units long is scaled to 20.7 units. For computational reasons, all stored dimensions in a layout database are typically expressed in integers. Therefore, in this example, the scaled edge is rounded to 21 units long, thus losing 0.3 units of accuracy. If the database resolution is decreased from 1 nm to 0.1 nm, then the scaled edge may be expressed as 207 units long at a 0.1 nm resolution, without loss of accuracy. In fact, it is typical that the manufacturing database has 10 times the resolution of the design database in anticipation of support for the shrink conversion to the half-node process. The 10 times resolution readily supports single significant digit scaling factors, such as 0.9, 0.8 or 0.7. To support two significant digit scaling factors, such as 0.75 or 0.71, the resolution in the manufacturing database needs to be two orders of magnitude greater than that of the design database. For this reason, the most frequently used scaling factor in the manufacturing database is 0.9, for approximately a 20% area reduction.
The scale and bias technique can only be applied to a “flat” database, however. The flat database is much larger than a hierarchical database, which is typically the form that is used for design. The flat database is not suitable for design use because of its size and also because modifying the layout in a flat database is difficult. If scaling is attempted in a hierarchical database, however, rounding errors may create connectivity problems, notches, jogs and small edges. Connectivity problems are detected in a layout versus schematic (LVS) check. Notches, jogs and small edges may be detected at a design rule check (DRC). For small blocks, such errors are few and manageable, and can be manually corrected. Correcting such errors is quite tedious and time consuming, nevertheless. For a medium to large circuit, the number of such errors may be prohibitively large for manual correction.
Conventional layout scaling requires the same scaling factor in both X and Y directions. In an advanced MOS fabrication process, circuit layout rules are driven by photo-lithographical limitations. One of the most important constraints is gate pitch, which is the center-to-center distance between the gates of two adjacent transistors. In an advanced process, the gates of neighboring transistors are required to have the same pitch or separation distance and further, such separation distance must be one of a limited number of pitches. Typically, all transistor gates are required to be aligned in the same direction. Such a requirement dictates the scaling factor applicable to the direction that is perpendicular to the alignment direction of the transistor gates. For example, if all gates of the transistors are aligned in the X direction, a fixed pitch is required between the gates in the Y direction. If the original process requires a gate pitch of 120 nm and the new process requires a gate pitch of 90 nm, then the scaling factor for the Y direction is 0.75. At the same time, if the transistor gates are aligned in the X direction, the transistor width after migration is determined by the X direction scaling factor. This scaling factor is significant, as the width of an MOS transistor is an important parameter that determines MOS circuit performance. Ideally, therefore, although the transistor gate pitch scaling factor (in this case the Y direction scaling factor) is determined by the process technology, the X direction scaling factor is determined by both process technology and design performance specifications. Thus, in most cases, the desired X and Y scaling factors are different. The different desired X and Y scaling factors make a traditional scale and bias method—which use the same X and Y scaling factors—ineffective for migrating real circuit design and layout.
Bias operations (i.e., growing or shrinking specific elements) are typically applied after the X and Y direction scaling operations are performed. The bias operations further refine the migration process to meet the requirements of the target process. In a lambda design rule system, all dimensions and design rules are scaled proportionally, which is not true of micron design rule systems that are used in practically almost all designs today. In a micron design rule system, although the design rules typically do not scale proportionally, the elements are scaled close to proportionality in general, so as to track an overall geometry shrinking scale. If the overall scaling for a given process is 70%, most dimensions and design rules would preferably be scaled around 70%. Consider a feature in the original layout measuring 90 nm in the X dimension. If the applicable scaling factor is 0.7, the resulting X dimension feature would be 63 nm after scaling. However, if the new design rule requires such a feature to be 65 nm, a bias operation is required to extend the feature by 2 nm, e.g., extending by 1 nm on each side in the X direction, in order to meet the new design rule. It is also often desirable to have different bias conditions in the X and Y directions. As scaling factors in the X and Y directions may be different, a square contact or via may become rectangular with unequal sides after scaling. Separate X and Y bias operations may be required to grow or shrink the migrated contact or via back to a square.
Most layout migration algorithms are based on layout compaction, which is a process that preserves the topology of the source layout. Typically, the user provides a technology file which describes the design rules of the target process. Since design rules have become very complicated for the advanced process, not all design rules can be coded into the technology file. In fact, for efficiency reason, often the basic design rules are the only ones coded in the technology file. Typically, the source layout is analyzed and each design rule is used as a constraint on all applicable elements in the layout. A reasonably optimized layout that satisfies these constraints can be obtained only by linear programming (LP) or graph-based algorithms. For a large layout, and as design rules have become increasingly complicated, even writing a technology file is a daunting task. Even a small block in a layout can result in applications of millions of constraints. Thus, even using linear programming or sophisticated techniques, the number of constraints and variables result in prohibitively long total runtime in a layout migration. Due to resource constraints, compaction algorithms are useful only on small circuits. As not all design rules can be coded into a technology file, manual corrections are inevitable for a complete layout migration. For medium to large circuits, the source layouts are divided into blocks and are migrated separately. The migrated blocks are subsequently integrated at the top-level. Even this top-level integration is not straightforward, as the operation may require further modifications of the already migrated lower-level blocks.
As a result, existing layout migration does not provide a complete solution, as the current methods can only work with a small block at a time and require integration of the migrated blocks.
Therefore, what is needed is a systematic approach to allow migration of entire layouts to new fabrication processes. Since existing layout migration tools can migrate only small, lower-level blocks efficiently, what is needed is a tool that can migrate the entire circuit efficiently, so as to eliminate the need for subsequent top-level integration. This approach must ensure that the migrated layout satisfies basic layout requirements, such as correct connectivity, transistor pitches, transistor gate lengths, metal widths, and contact or via sizes. The migrated circuit and layout should also satisfy a first-pass circuit performance requirement before further optimization is required. Such a migrated layout should be able to serve as a framework for lower-level block migrations using existing migration tools.
U.S. Pat. No. 5,640,497, entitled “LAYOUT REDESIGN USING POLYGON MANIPULATION” and U.S. Pat. No. 8,352,899, entitled “METHOD TO MODIFY AN INTEGRATED CIRCUIT (IC) DESIGN” each disclose layout modification. Other layout migration methods are disclosed, for example, in (a) U.S. Patent Application 20120304139, entitled “METHOD OF FAST ANALOG LAYOUT MIGRATION,” (b) U.S. Patent Application 20110161907, entitled “PRACTICAL APPROACH TO LAYOUT MIGRATION,” and (c) U.S. Patent Application 20130019219, entitled “SYSTEM AND METHOD FOR HIERARCHY RECONSTRUCTION FROM FLATTENED GRAPHIC DATABASE SYSTEM LAYOUT.”